1. Field of the Invention
The present invention relates to a digital delay line usable in particular in a voltage controlled oscillator (VCO) of a phase-locked loop (PLL) system.
2. Discussion of the Related Art
FIG. 1 is a diagram of a conventional embodiment of a digital VCO. The oscillator is controlled by a clock signal with frequency fx provided by a crystal, for example with a frequency of 270 MHz. The clock signal is provided to the clock input of a register 1. Registers or memories 2 and 3 store programmable respective values Q and P which are adjusted by the control signals of the VCO. The content of register 2 is transferred through an adder 4 to the D input of register 1 at the clock rate. The output Q of register 1 is provided to a first input of a digital comparator 5 and to a second input of the adder 4. The second input of comparator 5 receives the output P of register 3, and the comparator output provides the desired signal CLK and is applied as a reset input to register 1. Register 1 and adder 4 form an accumulator which is incremented by value Q at each clock pulse fx. So, when the multiplication of number Q has reached the value P, the comparator provides one signal pulse CLK. Therefore, this signal has a frequency F.sub.CLK =(Q/P)fx. Of course, this involves that P is higher than Q and even higher than 2Q. However, in fact, this circuit does not provide the frequency fx multiplied by Q/P but by the closest integer value higher than Q/P. In other words, there is a jitter of the same order of magnitude as the period of frequency fx.
To increase the oscillator accuracy and decrease the jitter, the frequency fx should be increased or the frequency F.sub.CLK should be smoothed at the oscillator output. In both cases, this involves the addition of an analog PLL to multiply the crystal frequency or to filter the oscillator's jitter. The use of such an analog loop is in contradiction with the realization of a fully digital VCO.
To solve this problem, it has already been proposed in the prior art (refer, for example, to IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, December 1990, pp. 1385-1394) to provide, as indicated in FIG. 2, from signals at frequency fx of a crystal, a plurality of signals phase-shifted by one n-th of the corresponding period, to provide respective signals of phase 1, of phase 2 . . . and of phase n. Then, as represented in FIG. 3, if the phase-i signal is used to provide one period of signal CLK, phase-i+1 signal (or another signal) can be used to generate the next period. In this case, the accuracy or jitter corresponds to the input signal period divided by the number of phases.
As represented in FIG. 4, the n phases can be introduced, for example, on n inputs of a multiplexer 10 used to generate the signal CLK. Multiplexer 10 is scanned at a variable frequency Fs to provide the frequency shift. Frequency Fs is directly proportional to the correction factor incoming from a filter stage normally integrated in a PLL. A bit rate multiplier 11, BRM, is designed to transfer the correction word in a scanning signal. The output of multiplier 11 is provided to an up-down counter (UDC) 12, whose up-counting or down-counting operation is determined by the most significant bit (MSB) which is the sign bit of the correction value of the filter.
In such a system, one problem lies in the realization of n signals accurately phase-shifted from signal fx. Up to now, and as indicated in the above mentioned article, these n shifted signals can be provided by a ring counter. However, the frequency of this ring counter has to be controlled to be independent of the manufacturing process, of temperature and of variations in the voltage parameters. Again, this control step involves the use of analog techniques.